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ltc4218 1 4218fe features applications description hot swap controller the ltc ? 4218 is a hot swap? controller that allows a board to be safely inserted and removed from a live backplane. an internal high side switch driver controls the gate of an external n-channel mosfet for supply voltages from 2.9v to 26.5v. a dedicated 12v version (ltc4218-12) contains preset 12v speci? c thresholds, while the standard ltc4218 allows adjustable thresholds. the ltc4218 provides an accurate (5%) current limit with current foldback limiting. the current limit threshold can be adjusted dynamically using an external pin. additional features include a current monitor output that ampli? es the sense voltage for ground referenced current sensing. overvoltage, undervoltage and power good monitoring are also provided. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 12v, 6a card resident application n wide operating voltage range: 2.9v to 26.5v n adjustable, 5% accurate (15mv) current limit n current monitor output n adjustable current limit timer before fault n power good and fault outputs n adjustable inrush current control n 2% accurate undervoltage and overvoltage protection n available in 16-lead ssop and 16-pin 5mm 3mm dfn packages n raid systems n atca, amc, tca systems n server i/o cards n industrial power-up waveform typical application adc 0.1f 12v 12v 20k 4218 ta01a 1k 10k auto retry 0.1f 0.01f 330f sense C gate sense + v dd uv source pg gnd i mon ltc4218dhc-12 intv cc timer flt 10 2m si7108dn v out 12v 6a + 25ms/div 4218 ta01b v in 10v/div i in 1a/div v out 10v/div pg 10v/div
ltc4218 2 4218fe 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 sense + sense C i set i mon fb flt pg gate nc v dd uv ov timer intv cc gnd source top view dhc package 16-lead ( 5mm s 3mm ) plastic dfn t jmax = 125c, ja = 43c/w exposed pad (pin 17) is substrate gnd gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 nc v dd uv ov timer intv cc gnd source sense + sense C i set i mon fb flt pg gate t jmax = 150c, ja = 135c/w pin configuration absolute maximum ratings supply voltage (v dd ) ................................. C0.3v to 35v input voltages fb, ov, uv ............................................. C0.3v to 12v timer ................................................... C0.3v to 3.5v sense C .............................v dd C 10v or C0.3v to v dd sense + .............................v dd C 10v or C0.3v to v dd source ........................................ C 5v to v dd + 0.3v output voltages i set , i mon ................................................. C0.3v to 3v pg, flt .................................................. C0.3v to 35v intv cc .................................................. C0.3v to 3.5v gate (note 3) ........................................ C0.3v to 35v (notes 1, 2) operating temperature range ltc4218c ................................................ 0c to 70c ltc4218i .............................................C40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) gn package only .............................................. 300c order information lead free finish tape and reel part marking* package description temperature range ltc4218cdhc-12#pbf ltc4218cdhc-12#trpbf 421812 16-lead (5mm 3mm) plastic dfn 0c to 70c ltc4218idhc-12#pbf ltc4218idhc-12#trpbf 421812 16-lead (5mm 3mm) plastic dfn C40c to 85c ltc4218cgn#pbf ltc4218cgn#trpbf 4218 16-lead plastic ssop 0c to 70c ltc4218ign#pbf ltc4218ign#trpbf 4218i 16-lead plastic ssop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc4218 3 4218fe electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. symbol parameter conditions min typ max units dc characteristics v dd input supply range l 2.9 26.5 v i dd input supply current fet on l 1.6 5 ma v dd(uvl) input supply undervoltage lockout v dd rising l 2.65 2.73 2.85 v v dd(uvth) input supply undervoltage threshold ltc4218-12 only v dd rising l 9.6 9.88 10.2 v v dd(uvhyst) input supply undervoltage hysteresis ltc4218-12 only l 520 640 760 mv v dd(ovth) input supply overvoltage threshold ltc4218-12 only v dd rising l 14.7 15.05 15.4 v v dd(ovhyst) input supply overvoltage hysteresis ltc4218-12 only l 183 244 305 mv v source(pgth) source power good threshold ltc4218-12 only v source rising l 10.2 10.5 10.8 v v source(pghyst) source power good hysteresis ltc4218-12 only l 127 170 213 mv v sns(th) current limit sense voltage threshold (v sense+ C v senseC ) v fb = 1.23v v fb = 0v v fb = 1.23v, r set = 20k l l l 14.25 2.8 6.7 15 3.75 7.5 15.75 4.7 8.325 mv mv mv i senseC(in) sense C pin input current v senseC = 12v l 4 10 a i sense+(in) sense + pin input current v sense+ = 12v l 5.5 20 a v gate external n-channel gate drive (v gate C v source ) v dd = 2.9v to 26.5v (note 3) i gate = 0, C1a l 5 6.15 6.5 v v gate-high(th) gate high threshold (v gate C v source ) l 3.5 4.2 4.8 v i gate(up) external n-channel gate pull-up current gate drive on, v gate = v source = 12v l C19 C24 C29 a i gate(fst) external n-channel gate fast pull-down current fast turn off, v gate = 18v, v source =12v l 100 170 220 ma i gate(dn) external n-channel gate pull-down current gate drive off, v gate = 18v, v source =12v l 200 250 340 a inputs i (in) ov, uv, fb pin input current v in = 1.2v, ltc4218 only l 01 a r (in) ov, uv, fb pin input resistance ltc4218-12 only l 13 18 23 k v (th) ov, uv, fb pin threshold voltage v in rising l 1.21 1.235 1.26 v v ov(hyst) ov pin hysteresis l 10 20 30 mv v uv(hyst) uv pin hysteresis l 50 80 110 mv v uv(rth) uv pin reset threshold voltage v uv falling l 0.55 0.62 0.7 v v fb(hyst) fb pin power good hysteresis l 10 20 30 mv r iset i set pin output resistor l 19.5 20 20.5 k i source source pin input current v source = v gate = 12v, ltc4218-12 only v source = v gate = 12v, ltc4218 only v source = v gate = 0v l l l 50 1 70 2 0 90 4 1 a a a outputs v (ol) pg, flt pin output low voltage i out = 2ma l 0.4 0.8 v i (oh) pg, flt pin input leakage current v out = 30v l 0 10 a v timer(h) timer pin high threshold v timer rising l 1.2 1.235 1.28 v v timer(l) timer pin low threshold v timer falling l 0.1 0.21 0.3 v i timer(up) timer pin pull up current v timer = 0v l C80 C100 C120 a i timer(dn) timer pin pull-down current v timer = 1.2v l 1.4 2 2.6 a
ltc4218 4 4218fe electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive, all voltages are referenced to gnd unless otherwise speci? ed. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. symbol parameter conditions min typ max units i timer(ratio) timer pin current ratio i timer(dn) / i timer(up) l 1.6 2 2.7 % i mon(fs) i mon full-scale output current v sense + C v sense C = 15mv l 94 100 106 a i mon(off) i mon pin offset current v sense + C v sense C = 1mv l 0 6 a g imon i mon pin gain v sense + C v sense C = 15mv and 1mv l 6.47 6.67 6.87 a/mv ac characteristics t phl(gate) input high (ov), input low (uv) to gate low propagation delay v gate < 16.5v falling l 35 s t phl(sense) v sense + C v sense C high to gate low propagation delay v fb = 0, step (v sense + C v sense C ) to 60mv, c gate = 1.5nf, v gate < 16.5v falling l 0.2 1 s t d(on) turn-on delay step v uv to 2v, v gate > 13v l 50 100 150 ms note 3: an internal clamp limits the gate pin to a maximum of 6.5v above the source pin. driving either gate or source pin to voltages beyond the clamp may damage the device.
ltc4218 5 4218fe typical performance characteristics i dd vs v dd intv cc load regulation uv low-high threshold vs temperature uv hysteresis vs temperature timer pull-up current vs temperature current limit delay current limit threshold foldback current limit adjustment i set resistor vs temperature t a = 25c, v dd = 12v unless otherwise noted. v dd (v) 0 1.0 i dd (ma) 1.2 1.4 1.6 1.8 2.0 5 101520 4218 g01 25 30 C40c 25c 85c i load (ma) 0 0 0.5 1.5 1.0 intv cc (v) 3.5 2.0 2.5 3.0 4218 g02 C14 C12 C10 C8 C6 C4 C2 v dd = 5v v dd = 3.3v temperature (c) C50 uv low-high hreshold (v) 1.234 1.232 1.230 1.228 1.226 C25 0 25 4218 g03 50 75 100 temperature (c) C50 uv hysteresis (v) 0.10 0.08 0.06 0.04 C25 0 25 4218 g04 50 75 100 temperature (c) C50 timer pull-up current (a) C110 C105 C100 C95 C90 C25 0 25 4218 g05 50 75 100 current limit sense voltage (v sense + C v sense C ) (mv) current limit propagation delay (s) 1000 100 10 1 0.1 075 4218 g06 15 30 45 60 c gate = 10nf fb voltage (v) 0 0 current limit sense voltage (v sense + C v sense C ) (mv) 4 8 2 6 10 12 14 16 0.2 0.4 0.6 0.8 4218 g07 1.0 1.2 r set () 1k current limit sense voltage (v dd C v sense ) (mv) 10k 100k 1m 4218 g08 10m 0 4 8 2 6 10 12 14 16 temperature (c) C50 r iset (k) 22 21 20 19 18 C25 0 25 4218 g09 50 75 100
ltc4218 6 4218fe typical performance characteristics gate drive vs temperature pg, flt v out low vs i load gate pull-up current vs temperature gate pull-up current vs gate drive gate drive vs v dd t a = 25c, v dd = 12v unless otherwise noted. i mon vs temperature and v dd i mon vs sense v imon vs sense temperature (c) C50 i gate pull-up (a) C26.0 C25.5 C25.0 C24.5 C24.0 C25 0 25 4218 g10 50 75 100 i gate (a) 0 0 gate drive (v gate C v source ) (v) 7 6 5 4 3 2 1 C5 C10 C15 C20 4218 g11 C25 C30 v dd = 12v v dd = 3.3v v dd (v) 0 6.2 6.0 5.8 5.6 5.4 5.2 51015 4218 g12 20 25 30 gate drive (v gate C v source ) (v) temperature (c) C50 6.15 6.14 6.13 6.12 6.11 6.10 C25 0 25 4218 g13 50 75 100 gate drive (v gate C v source ) (v) i load (ma) 0 0 pg, flt v out low (v) 14 12 10 8 6 4 2 2468 4218 g14 10 12 flt pg temperature (c) C50 105 100 95 90 85 80 C25 0 25 4218 g15 50 75 100 i mon (a) v dd = 3.3v, 12v, 24v v sense + C v sense C = 15mv sense voltage (mv) 0 0 i mon (a) 100 75 50 25 510 4218 g16 15 sense voltage (mv) 0 0 v imon (v) 4 3 2 1 510 4218 g17 15 r imon = 100k r imon = 40k r imon = 20k r imon = 10k
ltc4218 7 4218fe pin functions exposed pad: exposed pad may be left open or connected to device ground. fb: foldback and power good comparator input. connect this pin to an external resistive divider from source for the ltc4218 (adjustable version). the ltc4218-12 version uses a ? xed internal divider with optional external adjust- ment. open the pin if the ltc4218-12 thresholds for 12v operation are desired. if the voltage falls below 0.6v, the output power is considered bad and the current limit is reduced. if the voltage falls below 1.21v the pg pin will pull low to indicate the power is bad. flt : overcurrent fault indicator. open drain output pulls low when an overcurrent fault has occurred and the circuit breaker trips. for overcurrent auto-retry tie to uv pin (see applications information for details). gate: gate drive for external n-channel fet. an internal 24a current source charges the gate of the external n-channel mosfet. a resistor and capacitor network from this pin to ground sets the turn-on rate. during an undervoltage or overvoltage generated turn-off a 250a pull-down current turns the mosfet off. during a short circuit or undervoltage lockout, a 170ma pull-down current source between gate and source is activated. gnd: device ground. i mon : current monitor output. the current sourced from this pin is de? ned as the current sense voltage (between the sense + and sense C pins) multiplied by 6.67a/mv. placing a 20k resistor from this pin to gnd creates a 0v to 2v voltage swing when the current sense voltage ranges from 0mv to 15mv. intv cc : internal 3v supply decoupling output. this pin must have a 0.1f or larger capacitor. i set : current limit adjustment pin. for 15mv current limit threshold, open this pin. this pin is driven by a 20k resis- tor in series with a voltage source. the pin voltage is used to generate the current limit threshold. the internal 20k resistor and an external resistor between i set and ground create an attenuator that lowers the current limit value. nc: no connection ov: overvoltage comparator input. connect this pin to an external resistive divider from v dd for the ltc4218 (adjustable version). the ltc4218-12 version uses a ? xed internal divider with optional external adjustment for 12v operation. open the pin if the ltc4218-12 thresholds are desired. if the voltage at this pin rises above 1.235v, an overvoltage is detected and the switch turns off. tie to gnd if unused. pg: power good indicator. open drain output pulls low when the fb pin drops below 1.21v indicating the power is bad. sense C : current sense minus input. connect this pin to the opposite of v dd current sense resistor side. the cur- rent limit circuit controls the gate pin to limit the sense voltage between the sense + and sense C pins to 15mv or less depending on the voltage at the fb pin. sense + : current sense plus input. connect this pin to the v dd side of the current sense resistor. source: n-channel mosfet source connection. connect this pin to the source of the external n-channel mosfet switch. this pin provides a return for the gate pull-down circuit. in the ltc4218-12 version, the power good com- parator monitors an internal resistive divider between the source pin and gnd. timer: timer input. connect a capacitor between this pin and ground to set a 12ms/f duration for current limit before the switch is turned off. if the uv pin is toggled low while the mosfet switch is off, the switch will turn on again following a cool down time of 518ms/f duration. uv: undervoltage comparator input. tie high if unused. connect this pin to an external resistive divider from v dd for the ltc4218 (adjustable version). the ltc4218-12 version drives the uv pin with an internal resistive divider from v dd . open the pin if the preset ltc4218-12 thresholds for 12v operation are desired. if the uv pin voltage falls below 1.15v, an undervoltage is detected and the switch turns off. pulling this pin below 0.62v resets the overcurrent fault and allows the switch to turn back on (see applica- tions information for details). if overcurrent auto-retry is desired then tie this pin to the flt pin. v dd : supply voltage. this pin has an undervoltage lockout threshold of 2.73v.
ltc4218 8 4218fe functional diagram 4218 bd 20k v dd v dd v dd * * * * * dfn only uv fb pg exposed pad* i mon intv cc intv cc 100 a timer flt + C i set gate source gnd x1 clamp 0.6v reference charge pump and gate driver 3.1v gen logic cs cm foldback 0.6v 2.65v 1.235v +C + C pg 1.235v C + uv 0.2v C + tm1 1.235v C + tm2 0.62v C + rst v dd v dd 2.73v + C uvlo1 ov 1.235v C + ov 2 a C + uvlo2 sense C sense + source * * 150k 20k 140k 20k 224k 20k
ltc4218 9 4218fe operation the functional diagram displays the main circuits of the device. the ltc4218 is designed to turn a boards sup- ply voltage on and off in a controlled manner, allowing the board to be safely inserted and removed from a live backplane. during normal operation, the charge pump and gate driver turn on the external n-channel pass fets gate to provide power to the load. the current sense (cs) ampli? er monitors the load current using the voltage sensed across the current sense resistor. the cs ampli? er limits the current in the load by reducing the gate-to-source voltage in an active control loop. it is simple to adjust the current limit threshold using the current setting (i set ) pin. this allows a different threshold during other times such as startup. a short circuit on the output to ground causes signi? cant power dissipation during active current limiting. to limit this power, the foldback ampli? er reduces the current limit value from 15mv to 3.75mv (referred to the sense + minus sense C voltage) in a linear manner as the fb pin drops below 0.6v (see typical performance characteristics). if an overcurrent condition persists, the timer pin ramps up with a 100a current source until the pin voltage exceeds 1.2v (comparator tm2). this indicates to the logic that it is time to turn off the mosfet to prevent overheating. at this point the timer pin ramps down using the 2a current source until the voltage drops below 0.2v (comparator tm1) which tells the logic to start an internal 100ms timer. at this point, the pass transistor has cooled and it is safe to turn it on again. the ? xed 12v version, ltc4218-12, uses two separate internal dividers from v dd to drive the uv and ov pins. this version also features a divider from the source pin to drive the fb pin. the ltc4218-12 is available in a dfn package while the ltc4218 (adjustable version) is in a ssop package. the output voltage is monitored using the fb pin and the pg comparator to determine if the power is available for the load. the power good condition is signaled by the pg pin using an open-drain pull-down transistor. the functional diagram shows the monitoring blocks of the ltc4218. the comparators on the left side include the uv and ov comparators. these comparators are used to determine if the external conditions are valid prior to turning on the mosfet. but ? rst, the undervoltage lockout circuits (uvlo1 and uvlo2) must validate the input supply and internally generated 3.1v supply (intv cc ) and gener- ate the power up initialization to the logic circuits. if the external conditions remain valid for 100ms the mosfet is allowed to turn on. other monitoring features include the i mon current monitor. the current monitor (cm) outputs a current proportional to the sense resistor current. this current can drive an external resistor or other circuits for monitoring purposes.
ltc4218 10 4218fe applications information the typical ltc4218 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. the basic application circuit is shown in figure 1. external component selection is discussed in detail in the following sections. figure 2. supply turn-on figure 1. 3a, 12v card resident application turn-on sequence the power supply on a board is controlled by placing an external n-channel pass transistor (q1) in the power path. note the sense resistor (r s ) detects current and the capacitor (c gate ) controls gate slew rate. resistor r1 prevents high frequency oscillations in q1 and resistor r gate isolates c gate during fast turn-off. several conditions must be present before the external pass transistor can be turned on. first, the supply v dd must exceed its undervoltage lockout level. next, the internally generated supply intv cc must cross its 2.65v undervoltage threshold. this generates a 25s power- on-reset pulse which clears the logics fault register and initializes internal latches. after the power-on-reset pulse, the ltc4218 will go through the following sequence. first, the uv and ov pins must indicate that the input power is within the acceptable range. all of these conditions must be satis? ed for a duration of 100ms to ensure that any contact bounce during the insertion has ended. the pass transistor is turned on by charging up the gate with a 24a charge pump generated current source (figure 2). the voltage at the gate pin rises with a slope equal to 24a/c gate and the supply inrush current is set at: i inrush = c l c gate ?24a when the gate voltage reaches the mosfet threshold voltage, the switch begins to turn on and the source voltage follows the gate voltage as it increases. once source reaches v dd , the gate will ramp up until clamped by the 6.15v zener between gate and source. as the source pin voltage rises, so will the fb pin which is monitoring it. if the voltage across the current sense resistor (r s ) gets too high, the inrush current will be limited by the internal current limiting circuitry. once the fb pin crosses its 1.235v threshold and the gate to source voltage exceeds 4.2v, the pg pin will cease to pull low and indicate that the power is good. turn-off sequence the switch can be turned off by a variety of conditions. a normal turn-off is initiated by the uv pin going below its 1.235v threshold. additionally, several fault conditions will turn off the switch. these include an input overvoltage (ov pin) and overcurrent circuit breaker (sense pin). normally, the switch is turned off with a 250a current pulling down the gate pin to ground. with the switch turned off, the source pin voltage drops which pulls the fb pin below its threshold. the pg then pulls low to indicate output power is no longer good. r6 150k r7 20k adc r2 224k c1 0.1f r3 20k 12v 12v 4218 f01 r8 10k r1 10 c t 0.1f c l 330f v out 12v 3a v dd uv fb pg gnd i mon r set 20k r s 2m q1 si7108dn r mon 20k i set c gate 0.01f r gate 1k gate source sense C sense + ltc4218gn ov intv cc timer flt + r4 140k r5 20k t1 t2 slope = 24a/c gate gate source v dd + 6.15 v dd 4218 f02
ltc4218 11 4218fe applications information if v dd drops below 2.65v for greater than 5s or intv cc drops below 2.5v for greater than 1s, a fast shutdown of the switch is initiated. the gate is pulled down with a 170ma current to the source pin. overcurrent fault the ltc4218 features an adjustable current limit with foldback that protects the mosfet when excessive load current happens. to protect the switch during active cur- rent limit, the available current is reduced as a function of the output voltage sensed by the fb pin. a graph in the typical performance characteristics shows the current limit versus fb voltage. an overcurrent fault occurs when the current limit circuitry has been engaged for longer than the time-out delay set by the timer. current limiting begins when the current sense voltage between the sense + and sense C pins reaches 3.75mv to 15mv (depending on the foldback). the gate pin is then brought down with a 170ma gate-to-source current. the voltage on the gate is regulated in order to limit the current sense voltage to less than 15mv. at this point, a circuit breaker time delay starts by charging the external timing capacitor from the timer pin with a 100a pull-up current. if the timer pin reaches its 1.2v thresh- old, the external switch turns off (with a 250a current from gate to ground). next, the flt pin is pulled low to indicate an overcurrent fault has turned off the mosfet. for a given the circuit breaker time delay, the equation for setting the timing capacitors value is as follows: c t = t cb ? 0.083[f/ms] after the switch is turned off, the timer pin begins dis- charging the timing capacitor with a 2a pull-down current. when the timer pin reaches its 0.2v threshold, the switch is allowed to turn on again if the overcurrent fault has been cleared. bringing the uv pin below 0.6v and then high will clear the fault. if the timer pin is tied to intv cc , then the switch is allowed to turn on again (after an internal 100ms delay) if the overcurrent fault is cleared. tying the flt pin to the uv pin allows the part to self-clear the fault and turn the mosfet on as soon as timer pin has ramped below 0.2v. in this auto retry mode, the ltc4218 repeatedly tries to turn on after an overcurrent at a period determined by the capacitor on the timer pin. the waveform in figure 3 shows how the output latches off following a short circuit. the drop across the sense resistor is 3.75mv as the timer ramps up. figure 3. short-circuit waveform current limit adjustment the default value of the active current limiting signal threshold is 15mv. the current limit threshold can be adjusted lower by placing a resistor on the i set pin. as shown in the functional diagram the voltage at the i set pin (via the clamp circuit) sets the cs ampli? ers built-in offset voltage. this offset voltage directly determines the active current limit value. with the i set pin open, the volt- age at the i set pin is determined by the buffered reference voltage. this voltage is set to 0.618v which corresponds to a 15mv current limit threshold. an external resistor placed between the i set pin and ground forms a resistive divider with the internal 20k sourcing resistor. the divider acts to lower the voltage at the i set pin and therefore lower the current limit threshold. the overall current limit threshold precision is reduced to 11% when using a 20k resistor to half the threshold. using a switch (connected to ground) in series with the external resistor allows the active current limit to change only when the switch is closed. this feature can be used when the startup current exceeds the typical maximum load current. 1ms/div 4218 f03 $ v gate 10v/div i out 2a/div v out 10v/div timer 2v/div
ltc4218 12 4218fe applications information monitor mosfet current the current in the mosfet passes through the sense resistor. the voltage on the sense resistor is converted to a current that is sourced out of the i mon pin. the gain of the i sense ampli? er is 100a from i mon for 15mv on the sense resistor. this output current can be converted to a voltage using an external resistor to drive a comparator or adc. the voltage compliance for the i mon pin is from 0v to intv cc C 0.7v. a microcontroller with a built-in comparator can build a simple integrating single-slope adc by resetting a capaci- tor that is charged with this current. when the capacitor voltage trips the comparator and the capacitor is reset, a timer is started. the time between resets will indicate the mosfet current. monitor ov and uv faults protecting the load from an overvoltage condition is the main function of the ov pin. in the ltc4218-12 an internal resistive divider (driving the ov pin) connects to a compara- tor to turn off the mosfet when the v dd voltage exceeds 15.05v. if the v dd pin subsequently falls back below 14.8v, the switch will be allowed to turn on immediately. in the ltc4218, the ov pin threshold is 1.23v when rising and 1.21v when falling out of overvoltage. the uv pin functions as an undervoltage protection pin or as an on pin. in the ltc4218-12 the mosfet turns off when v dd falls below 9.23v. if the v dd pin subsequently rises above 9.88v for 100ms, the switch will be allowed to turn on again. the ltc4218 uv turn on/off threshold is 1.23v (rising) and 1.15v (falling). in the case of an undervoltage or overvoltage, the mosfet turns off and there is indication on the pg status pin. when the overvoltage is removed, the mosfets gate ramps up immediately. power good indication in addition to setting the foldback current limit threshold, the fb pin is used to determine a power good condition. the ltc4218-12 uses an internal resistive divider on the source pin to drive the fb pin. the pg comparator in- dicates logic high when source pin rises above 10.5v. if the source pin subsequently falls below 10.3v, the com- parator toggles low. on the ltc4218, the pg comparator drives high when the fb pin rises above 1.23v and low when falls below 1.21v. once the pg comparator is high, the gate pin voltage is monitored with respect to the source pin. once the gate minus source voltage exceeds 4.2v, the pg pin goes high. this indicates to the system that it is safe to load the output while the mosfet is completely turned on. the pg pin goes low when the gate is commanded off (using the uv, ov or sense + /sense C pins) or when the pg comparator drives low. 12v fixed version in the ltc4218-12, the uv, ov and fb pins are driven by internal dividers which may need to be ? ltered to prevent false faults. by placing a bypass capacitor on these pins the faults are delayed by the rc time constant. use the r in value from the electrical table for this calculation. in cases where the ? xed thresholds need a slight adjust- ment, placing a resistor from the uv or ov pins to v dd or gnd will adjust the threshold up or down. likewise, placing a resistor between fb pin to out or gnd adjusts the threshold. again, use the r in value from the electrical table for this calculation. an example in figure 4 raises the uv turn-on voltage from 9.88v to 10.5v. increasing the uv level requires adding a resistor between uv and ground. the resistor, (r shunt1 ), can be calculated using electrical table parameters as follows: r shunt1 = r in () ?v old v new ?v old () = 18k ? 9.88 10.5 ? 9.88 () = 287k figure 4. adjusting ltc4218-12 thresholds 4218 f04 ltc4218-12 r shunt1 r shunt2 v dd ov uv
ltc4218 13 4218fe applications information in this same ? gure the ov threshold is lowered from 15.05v to 13.5v. decreasing the ov threshold requires adding a resistor between v dd and ov. this resistor can be calculated as follows: r shunt2 = r in () ?v old v th () v new ?v ov th () () v old ?v new () ? ? ? ? ? ? ? ? ? ? = 18k ? 15.05 1.235 13.5 ? 1.235 () 15.05 ? 13.5 () ? ? ? ? ? ? = 1.736m use the equation for r shunt1 for increasing the ov and fb thresholds. likewise, use the equation for r shunt2 for decreasing the uv and fb thresholds. design example consider the following design example (figure 5): v in = 12v, i max = 7.5a. i inrush = 1a, c l = 330f, v uvon = 9.88v, v ovoff = 15.05v, v pwrgd = 10.5v. a current limit fault trig- gers an automatic restart of the power up sequence. the selection of the sense resistor, (r s ), is set by the overcurrent threshold of 15mv: r s = 15mv/i max = 15mv/7.5a = 0.002 the mosfet should be sized to handle the power dissi- pation during the inrush charging of the output capacitor c out . the method used to determine the power in q1 is the principal: e c = energy in c l = energy in q1 thus: e c = ? cv 2 = ? (330f)(12) 2 = 0.024j calculate the time it takes to charge up c out : t chargup = c l ?v in i inrush = 330f ? 12v 1a = 4ms the inrush current is set to 1a using c gate : c gate = c l i gate(up) i inrush = 330f 24a 1a ? 0.01f the average power dissipated in the mosfet: p diss = e c /t chargup = 0.024j/4ms = 6w the soa (safe operating area) curves of candidate mos- fets must be evaluated to ensure that the heat capacity of the package can stand 6w for 4ms. the soa curves of the vishay siliconix si7108dn provide 1.5a at 10v (15w) for 100ms, satisfying the requirement. figure 5. 6a, 12v card resident application 12v c t 0.1f adc c1 0.1f r3 20k 4218 f05 r2 10k c l 330f sense C gate sense + v dd uv source pg gnd i mon ltc4218dhc-12 intv cc timer flt r1 10 r s 2m q1 si7108dn 12v + v out 12v 6a r gate 1k c gate 0.01f
ltc4218 14 4218fe applications information next, the power dissipated in the mosfet during overcur- rent must be limited. the active current limit uses a timer to prevent excessive energy dissipation in the mosfet. the worst-case power occurs when the voltage versus current pro? le of the foldback current limit is at the maximum. this occurs when the current is 6a and the voltage is one half of 12v or (6v). see the current limit sense voltage vs fb voltage in the typical performance curves to view this pro? le. in order to survive 36w, the mosfet soa dictates a maximum time at this power level. the si7108dn allows 60w for 10ms or less. therefore, it is acceptable to set the current limit timeout using c t to be 1.2ms: c t = 1.2ms/12[ms/f] = 0.1f after the 1.2ms timeout the flt pin needs to pull down on the uv pin to restart the power-up sequence. since the default values for overvoltage, undervoltage and power good thresholds for the 12v ? xed version match the requirements, no external components are required for the uv, ov and fb pins. the ? nal schematic results in very few external com- ponents. resistor r1 (10 ) prevents high frequency oscillations in q1 while r gate of 1k isolates c gate during fast turn-off. the pull-up resistor, (r2), connects to the pg pin while the 20k (r3) converts the i mon current to a voltage at a ratio: v a mv mv a ki imon out = ? ? ? ? ? ? ? ? ? ? ? ? = 6 67 2 20 0 .???. 2 267 v a i out ? ? ? ? ? ? ? in addition, there is a 0.1f bypass (c1) on the intv cc pin. layout considerations to achieve accurate current sensing, a kelvin connection for the sense resistor is recommended. the pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistors and the power mosfets should include good thermal management techniques for optimal device power dissipa- tion. a recommended pcb layout for the sense resistor and power mosfet is illustrated in figure 6. in hot swap applications where load currents can be 6a, narrow pcb tracks exhibit more resistances than wider tracks and operate at elevated temperatures. the minimum trace width for 1oz copper foil is 0.02 per amp to make sure the trace stays at a reasonable temperature. using 0.03 per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 0.5m /square. small resistances add up quickly in high current applications. figure 6. recommended layout 4218 f06 r1 r s c q1 ltc4218
ltc4218 15 4218fe figure 7. 3.3v, 6a card resident application applications information it is also important to put c1, the bypass capacitor for the intv cc pin, as close as possible between the intv cc and gnd. place the 10 resistor as close as possible to q1. this will limit the parasitic trace capacitance that leads to q1 self-oscillation. additional applications the ltc4218 has a wide operating range from 2.9v to 26.5v. the uv, ov and pg thresholds are set with a few c t 0.1f c1 0.1f r5 14.7k r6 10k r2 17.4k adc r3 3.16k r4 10k 3.3v r mon 20k 4218 f07 r7 10k c l 330f sense C gate sense + v dd uv source fb pg gnd i out ltc4218gn ov intv cc timer flt r1 10 r s 2m q1 si7102dn 3.3v + r gate 1k c gate 0.01f v out 3.3v 6a resistors. all other functions are independent of supply voltage. the last page includes a 24v application with a uv threshold of 19.8v, an ov threshold of 28.3v and a pg threshold of 20.75v. figure 7 shows a 3.3v applica- tion with a uv threshold of 2.87v, an ov threshold of 3.77v and a pg threshold of 3.05v. figure 8 shows a backplane resident application, where load insertion activates turn-on. figure 8. 12v, 6a backplane resident application with insertion activiated turn -on c t 0.1f c1 0.1f r3 20k r4 140k r2 150k adc 12v 12v load r mon 20k 4218 f08 r8 10k sense C gate sense + v dd uv source fb pg gnd i mon ltc4218gn ov intv cc timer flt r1 10 r s 2m q1 si7108dn r gate 1k c gate 0.01f v out 12v 6a r5 20k
ltc4218 16 4218fe package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05 gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 15 14 13 .189 ? .196* (4.801 ? 4.978) 12 11 10 9 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .007 ? .0098 (0.178 ? 0.249) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc4218 17 4218fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number d 12/09 revised order information. revised equation in applications information. 2 14 e 04/10 revised storage temperature range in absolute maximum ratings section. revised additional applications section and inserted figure 8 in applications information. 2 15 (revision history begins at rev d)
ltc4218 18 4218fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0410 rev e ? printed in usa typical application 24v, 6a card resident application related parts part number description comments ltc1421 dual channel, hot swap controller operates from 3v to 12v, supports C12v, ssop-24 ltc1422 single channel, hot swap controller operates from 2.7v to 12v, so-8 ltc1642a single channel, hot swap controller operates from 3v to 16.5v, overvoltage protection up to 33v, ssop-16 ltc1645 dual channel, hot swap controller operates from 3v to 12v, power sequencing, so-8 or so-14 ltc1647-1/ltc1647-2/ ltc1647-3 dual channel, hot swap controllers operates from 2.7v to 16.5v, so-8 or ssop-16 ltc4210 single channel, hot swap controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4211 single channel, hot swap controller operates from 2.5v to 16.5v, multifunction current control, msop-8 or msop-10 ltc4212 single channel, hot swap controller operates from 2.5v to 16.5v, power-up timeout, msop-10 ltc4214 negative voltage, hot swap controller operates from C 6v to C16v, msop-10 ltc4215 single hot swap controller with adc and i 2 c interface operates from 2.9v to 15v, digitally monitors voltage and current with 8-bit adc lt4220 positive and negative voltage, dual channel, hot swap controller operates from 2.7v to 16.5v, ssop-16 ltc4221 dual hot swap controller/sequencer operates from 1v to 13.5v, multifunction current control, ssop-16 ltc4230 triple channel, hot swap controller operates from 1.7v to 16.5v, multifunction current control, ssop-20 ltc4245 quad hot swap controller with adc and i 2 c interface 3.3v, 5v and 12v for compactpci, or 3.3v, 3.3v auxiliary and 12v for pci- express, monitors voltage and current with 8-bit adc 158k 10k 215k adc 4.32k 0.1f 10k 24v 20k 4218 ta02 * *diodes inc., smaj24a 10k 0.1f 330f sense C gate sense + v dd uv source fb pg gnd i mon ltc4218gn ov intv cc timer flt 10 si7788dp 24v 2m + 1k 0.01f v out 24v 6a

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